As semiconductor devices reach higher levels of integration, packaging technologies, such as chip bonding and wafer-level bonding, have become critical. Packaging of the IC chip accounts for a considerable portion of the cost of producing the device and failure of the package leads to costly yield reduction. As semiconductor device sizes have decreased, the density of devices on a chip has increased, along with the size of the chip, thereby making chip bonding more challenging. One of the major problems leading to package failure as chip sizes increase is the increasingly difficult problem of maintaining solid structural and electrical connections between contact/bonding pads on the two components being bonded together. For example, in flip-chip techniques, solder joints between the IC chip and the package substrate after the structures have been metallurgically bonded together may suffer structural deficiencies. The most common technique for improving the strength of the bond between the IC chip and the package substrate is the inclusion of an “underfill” material between the two and around the ball grid array (BGA) comprised of solder balls or bumps used to bond the two components.
The underfill material, which is a dielectric material, is typically injected or otherwise placed between the two components (e.g., an IC chip and a package substrate), and around the solder bumps forming the BGA bonding the two. Unfortunately, the underfill process often makes the assembly of electronic packages, a labor intensive, time consuming, and expensive process. The underfill process reduces production efficiency because the injecting and subsequent curing of the encapsulant material is a multi-step process, which requires the material to flow through tiny gaps between the two substrates being bonded. Also, as IC chip sizes increase, the flowing of the encapsulant material takes even more time, and becomes more susceptible to void formation when the density of the BGA increases, as with more complex chips. More specifically, as the pitch between adjacent solder bumps used to bond the two substrates decreases, uniform flow of encapsulant between the two substrates becomes even more difficult. Because voids are often the center of stress concentrations, and the residual gases inside such voids may expand when heated and cause damage, reliability of the electronic package is all too often an issue.